Conventional semiconductor device packages comprise an integrated circuit or chip or die mounted on a substrate. Typically, the die is mounted on the substrate and interconnections are formed by wire bond and/or flip chip techniques as known in the art. In either case, the die does not cover the entire surface area of the substrate. Additional components such as decoupling capacitors or other passive circuit elements are also usually included within the package, typically on the substrate area surrounding the die, in order to reduce noise and high frequency transients on the die, for example. A stiffener is used to provide stability to the package elements, and prevent warpage due to thermal expansion.
Conventionally, the stiffener is mounted on the substrate using surface mount technology (SMT). Stiffeners can be made from metals such as Copper or Aluminum or a ceramic material. The coefficient of thermal expansion (CTE) of the stiffeners can be made to match that of the substrate in order to provide mechanical support and prevent warpage.
A schematic top view as well as a pictorial depiction of conventional package 100 is illustrated in FIG. 1. One or more dies, collectively depicted as die 104, is mounted on substrate 102. Substrate 102 may include passives 106 in an outer perimeter around die 104. Passive 106 and other components may be mounted on substrate 102 using SMT. Stiffener 108 surrounds substrate 102 in an outer ring. A horizontal portion of stiffener 108 overlaps the surface of substrate 102 and a substantial horizontal area of stiffener 108 lies outside the horizontal surface area of substrate 102 in order to provide mechanical stability. Stiffener 108 may also be attached or mounted on substrate 102 using SMT.
The structure of conventional package 100 suffers from many drawbacks. Stiffener 108 has a large horizontal area or thickness which extends beyond the horizontal area of substrate 102 in order to satisfy the requirements of protecting the package components (sometimes greater than 0.5 mm). This increases the overall footprint or horizontal surface area of the package. However, advancements in technology place demands on significant reduction in the size and area of packages, which in turn imposes a restriction on useful package area, i.e., package area not consumed by the stiffener. High end surface mount packaging, such as, the well-known flip chip ball grid array (fcBGA) are further seen to require smaller package thickness in order to maintain a thin package profile. Such technologies are seen suffer from the limitation on package components which can be included and also rising package thicknesses, owing to the conventional stiffener structures which are currently used.
Some conventional approaches attempt to overcome the above limitations by creating holes in the surface-mounted stiffener material in order to create room for integration of passive components in these holes. However, these holes disrupt continuity of the stiffener, which reduces the stiffener's effectiveness in providing mechanical stability and preventing warpage. Moreover, electrical connections to these passives formed within the holes in the stiffener, or other conventional placements of the passive components (e.g., passives 106) require careful and meticulous planning because of their scattered placement on the substrate, with a view to maximizing available surface area on the substrate. This also affects the power distribution network (PDN) design for the package, as expensive and often difficult wiring paths need to be created to accommodate such placement of the passives.
Accordingly, there is a need for overcoming the aforementioned problems associated with conventional stiffener structures, in order to achieve high quality stiffener structures which do not negatively impact the package sizes.